Synchronous systems provide many advantages in design and use. Pacing the system with a global clock enhances robustness and simplifies the logic design by making timing restrictions single bound. Lower bound delay problems are taken care of by the clock system. As system clock speeds have increased, clock buffer delays have created problems in that clock signals are not switching simultaneously everywhere in the system. This can be overcome to varying degrees by three types of improvements:
1) At moderately high clock frequencies the delays associated with on-chip clock buffering dominates. This means the clock signals actually clocking flip-flops and/or other clocks elements on the circuits lag the global reference clock substantially. By the use of a PLL based on-chip clock buffer system the delays associated with clock buffering and on-chip clock distribution can be canceled. PA1 2) When even higher speed data signals are sent over some distance in general, and from one circuit to another in particular, signal delays can render the use of a global synchronous clock impossible. The finite signal propagation velocity in electrical or optical distribution makes the concept of contemporaneousness or simultaneity meaningless. Often, this limitation is overcome by the use of a synchronization circuitry, adaptively adjusting the phase relation between clock and data signal at the destination, in the receiver's phase domain. Synchronization circuitry, increases system cost and power consumption. PA1 3) For high frequency signals sent over fairly short distances in controlled signalling environments, a more simple solution is possible. The problem of strobing or clocking the data signal at the proper instant can be overcome by sending both a data and a clock signal from the data source to the destination via carefully delay matched wiring. This clock signal is used in the receiver for strobing data at times when the data has valid logic levels only.
A typical application according to prior art using clock and data transfer is demonstrated in FIG. 1, which is an all differential signal implementation.
Modern integrated circuit technology allows higher and higher clock frequencies to be used for the data transfers. This puts higher and higher demands on matching of all delays in the signal paths for clock and data. The different nature of clock and data signals presents a difficulty in generating clock and data signals with perfect matching of pulse edge positions. Data signals have their edge positions controlled from a clock signal via a flip-flop. To generate a clock signal with matched edge positioning is difficult. Wherever possible, identical circuit elements are used for accomplishing matched delays. To generate the clock signal also from the output of a flip-flop, would require a 2.times. frequency source clock signal, since the output of a flip-flop can only change in response to one of the edges of the signal connected to the flip-flop clock input. In high speed applications, however, clock frequencies have already been pushed to the limits of the process technology. In an implementation according to FIG. 1, that speed could not be reached because the receiving flip-flop FR will not be clocked near the optimum points in the data pattern.
In FIG. 2 the signal timing for a particular set of operating conditions A, is shown. Here, it would seem safe to use the rising edge of clock C5 for clocking the data signal D5 into flip-flop FR, whereas the negative edge of C5 would not yield stable results when taking set up time t.sub.su into consideration. However, this statement is based on a single observation only.
In FIG. 3 processing, voltage and/or temperature are assumed to have changed such that the gate delays and thus t.sub.su in the circuits are doubled. Now, it is clear that the negative edge of clock C5 would be preferred instead of the positive edge for clocking data D5 at the receiving flip-flop FR, as was the case in FIG. 2. Hence, it is important to consider the variations of gate delays due to varying operational conditions in order to achieve maximum operating frequency.
In order to have reliable operation at high speed signalling under varying operating conditions, the variation in the strobe point relative to the received data signal must be minimized. Since the transmitting and receiving circuits can be operating together under different conditions in terms of processing, voltage and temperature, tracking can only be achieved if transmitter delays are compensated for in the transmitter circuit, and receiver delays are compensated in the receiver circuit. The only delay difference on the transmitter clock and data outputs that does not vary with operating conditions is zero.
The circuit of FIG. 1 has a delay difference on the clock and data outputs equal to the delay of the clock C1 to the Q output of the FT flip-flop. For delay compensation, the clock signal(s) must be delayed by the same amount. A carefully laid out replica of the elements making up the clock to Q delay inside the flip-flop FT, can achieve this if built next to the flip-flop in the same circuit, such that the operating conditions are the same. However, the very nature of a flip-flop makes it difficult to achieve minute matching without also dividing the clock signal frequency by two.
In several prior art documents treating synchronization, a global clock signal frequency has been increased so much that the concept of contemporaneity is no longer meaningful. The clock signals at the different destinations are isochronous (correct frequency, but arbitrary phase), but not synchronous. Several documents, for example EP-B1-0 356 042, DE-A1-4 132 325, U.S. Pat. No. 5 022 056, U.S. Pat. No. 5 115 455 and U.S. Pat. No. 5 359 630, describe different ways of handling this uncertainty in phase. All of these utilize multiplexers, but not for retiming. The select inputs are used to select one of the data inputs to the multiplexer, to have said inputs control timing of transitions on the output.
Particularly the last two references may be considered as closely related to the present invention, but in spite of a clock signal being sent from the same place as the data signal no attempt is made to match the delays. Instead a complicated synchronization function is used at the receiving side.